Computer 03

HPC: Future Technology Building Blocks

Tuesday, June 1, 2010, 9:00am – 10:30am, Hall B2.1

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Chair

  • John Shalf, Advanced Technology Group Leader, Lawrence Berkeley National Laboratory/NERSC, USA

Over the past forty years, progress in supercomputing has consistently benefitted from improvements in integrated circuit scaling according to Moore’s law, which has yielded exponential improvements in peak system-level floating point performance. For as long as the Top500 list has been in existence, HPC system measured LINPACK performance has consistently increased by a factor of 1000x every 11 years. Moore's law has supplied 100x of that improvement, but the extra 10x has been delivered through innovations that are specific to the leading-edge HPC architectural space.

However, changes in device physics threaten further sustained progress of extreme-scale HPC systems. For the first time in decades, the advances in computing technology are now threatened, because while transistor density on silicon is projected to increase with Moore’s Law, the energy efficiency of silicon is not. Power has rapidly become the leading design constraint for future HPC systems systems. Numerous studies conducted by DOE-ASCR(1), DOE-NNSA(2) and DARPA(3) have concluded that given these new constraints, the current approach to designing leading-edge HPC systems is unsustainable – leading to machines consuming upwards of 60 megawatts.

New approaches will not emerge from evolutionary changes in processor speed and scale from today’s petascale systems, but will require fundamental breakthroughs in hardware technology, programming models, algorithms, and software at both the system and application level. The Top500 list predicts emergence of an Exaflop-scale computing system by 2019. Given these daunting technology challenges, continuation of historical growth rates in HPC are by no means certain.

We have invited three leaders in the field of HPC system technology to discuss component technologies that are on the critical path for delivering effective and power efficient extreme-scale computing systems over the next decade. The speakers will cover a range of approaches to mitigating the major technology roadblocks that were identified in recent studies by DARPA, DOE, and the International Exascale Software Project. Specifically, the speakers will address technology challenges of memory, interconnect, and technologies for fault resilience that are essential for maintaining the historical 1000x growth rate in HPC performance within the next decade.

  • Dr. Dean Klein, VP of Memory System Development at Micron Memory Technology, will discuss advanced memory technology to increase the density, performance, and energy efficiency of memory technology.
  • Prof. Dr. Luca Carloni from the Columbia University’s Lightwave Research Laboratory, will describe silicon photonic technologies that are on the critical path for enabling energy-efficient and globally high-bandwidth communication across large systems.
  • Dr. Steve Scott, CTO of Cray Inc., will describe HPC system architecture and system integration challenges for extreme-scale systems, with a focus on fault resilience and scalable system technologies.

(1) DOE E3 Report: http://www.er.doe.gov/ascr/ProgramDocuments/ProgDocs.html
(2) A Platform Strategy for the Advanced Simulation and Computing Program” (NA-ASC-113R-07-Vol. 1-Rev. 0)
(3) DARPA Exascale Computing Study (TR-2008-13): http://www.cse.nd.edu/Reports/2008/TR-2008-13.pdf