Dr. Avinash Palaniswamy (Nash)
Senior Manager Throughput Computing, Intel, USA
Dr. Nash has been at Intel since October 2005, and focuses in the areas of High-End HPC and Throughput Computing in the Datacenter group. His responsibilities include the strategy and marketing efforts around High-End HPC hardware and software solutions, Intel® QuickAssist Technology enabled Accelerators, and other technologies related to throughput computing. His prior responsibilities at Intel included being the World Wide Web Consortium Advisory Committee representative from Intel. Prior to joining Intel as part of the acquisition of Conformative Systems, an XML Accelerator Company, he has served in several senior executive positions in the industry including being the Director of System Architecture at Conformative Systems, CTO/VP of Engineering at MSU Devices, and Director of Java Program Office and Wireless Software Strategy in the Digital Experience Group of Motorola, Inc. Dr. Palaniswamy holds a B.S. in Electronics and Communications Engineering from Anna University (Chennai, India) and an M.S. and Ph.D. from the University of Cincinnati in Electrical and Computer Engineering.