Contribution Details |
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| Name: |
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BoF 5: Preparing for Exascale: Rehearsing for Extreme Parallelism Does Pay Off |
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Tuesday, June 19, 2012
2:15 PM - 3:00 PM |
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Hall C2.1
CCH - Congress Center Hamburg |
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Hans-Christian Hoppe, Intel |
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Marie-Christine Sawley, Intel |
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| Abstract: |
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To the best of our knowledge, applications on future processors on the way to Exascale must fully exploit both data and task parallelism. The message from CPU architects for application developers has consistently been to work on parallelization and vectorization. A good example for future processors is the Intel® Many Integrated Core architecture, which offers a high degree of threaded parallelism combined with very capable SIMD execution units. The availability of Intel ® MIC SDVs for selected partners, and the announcement of a first Intel ® MIC product has met with significant interest from the HPC community and did trigger a lot of innovative code development work. The Intel European Exascale Labs are involved at the forefront of this, and they engage in leading edge software co-design activities with a number of partners to explore the potential of such architectures and inform their development. This BoF is the opportunity to share the first experiences, and to discuss how these resonate with the larger HPC community. We are convinced that the work on applications for the leap to Exascale will pay off in the shorter term by making applications more performant on the full range of HPC systems today and tomorrow. |
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