Steve OberlinChief Technology Officer, Accelerated Computing, NVIDIA
Steve Oberlin’s large-scale computing technology career has spanned over 30 years, launched in 1980 at Cray Research bringing up CRAY-1 supercomputer systems. Starting in 1981, he worked for Seymour Cray as a designer and project engineer on the CRAY-2 and CRAY-3 supercomputers. Design credits include the CRAY-2 floating-point multiply/reciprocal/square root functional units, high-speed SRAM memory tester, and Cray’s first at-speed module tester. In 1988, he led early massively parallel processing research at Cray that ultimately led to his role as the chief architect of the CRAY T3D MPP and its successor, the CRAY T3E. Steve was named Director of the MPP Project in 1994 and led the development of the next-generation Scalable Node supercomputing architecture. He holds 15 communications, synchronization, and design patents for the T3D and T3E.
Steve was VP of Hardware Engineering in Chippewa Falls, Wisconsin, for Cray/SGI from 1996 until early 1999, responsible for hardware development and support of all Cray products and their follow-ons, including the T3E, T90, J90 and SV1, and the future SV2. He was then named VP of Software Engineering for SGI, a position he held until being named GM of the Cray Research Business Unit while SGI sought a buyer.
Steve left SGI to found Unlimited Scale, Inc., in July of 2000 and served as Unlimited Scale’s President and CEO until USI was acquired during the formation of Cassatt in August 2003. He was the EVP of Product Development until May 2004, when he was named Cassatt’s EVP/Chief Scientist. In June 2009, he joined CA, Inc. (formerly Computer Associates), when CA purchased Cassatt’s cloud-related IP and technology, spending the next three and a half years as a Sr. VP/Distinguished Engineer in the CTO office developing next-generation cloud-oriented resource optimization architectures applying machine learning.
Steve joined NVIDIA in November 2013. As CTO for Accelerated Computing, he is responsible NVIDIA’s Tesla roadmap and architecture.