|Name:||(14a) Performance Evaluation of SpMV Considering Matrix Layout Parameters|
|Time:||Thursday, June 26, 2014
10:30 am - 11:00 am
CCL - Congress Center Leipzig
|Breaks:||10:30 am - 11:00 am Coffee Break|
07:30 am - 10:30 am Welcome Coffee
|Presenter:||Satoshi Ohshima, University of Tokyo|
|Abstract:||In current supercomputer systems, various kinds of parallel computation units are used. Each hardware has different architecture and corresponding performance trends respectively. Accelerating of sparse matrix-vector multiplication (SpMV) is required because its computation is dominant part of various scientific applications. Therefore, the author and research group deal with analyzing and accelerating the SpMV on various computation environment. The author showed the performance of SpMV using CRS format and ELL format on various hardware at HPC in Asia Poster at ISC'13 and now we are continuing such research activities.
This poster focuses on the relationship between performance and matrix layout parameters.
Satoshi Ohshima, University of Tokyo