Thursday Keynote
Fooling the Masses with Performance Results: Old classics & Some New Ideas 

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Thursday, June 20, 12:15 pm - 1:00 pm, Hall 1

Prof. Dr. Gerhard Wellein
Head of High Performance Computing Group, Erlangen Regional Computing Center, Germany

In 1991, David H. Bailey published his insightful "Twelve Ways to Fool the Masses When Giving Performance Results on Parallel Computers." In that humorous article, Bailey pinpointed typical “evade and disguise” techniques for presenting mediocre performance results in the best possible light. At that time, the supercomputing landscape was governed by the "chicken vs. oxen" debate: Could strong vector CPUs survive against the new massively parallel systems? In the past two decades, hybrid, hierarchical systems, multi-core processors, accelerator technology, and the dominating presence of commodity hardware have reshaped the landscape of High Performance Computing. It’s also not so much oxen vs. chickens anymore; billions of ants have entered the field. This talk gives an update of the "Twelve Ways." Old classics are presented alongside new "stunts" that reflect today's technological boundary conditions.

DISCLAIMER: Although these musings are certainly inspired by experience with many publications and talks in HPC, I wish to point out that (i) no offense is intended, (ii) I am not immune to the inherent temptations myself and (iii) this all still just meant to be fun.

Links:
http://blogs.fau.de/hager/category/fooling-the-masses/
http://crd-legacy.lbl.gov/~dhbailey/dhbtalks/dhb-12ways.pdf

 

Gerhard Wellein holds a PhD in solid state physics from the University of Bayreuth, Germany and is a professor at the Department for Computer Science at the University of Erlangen-Nuremberg. He leads the HPC group at Erlangen Regional Computing Center (RRZE) and has more than ten years of experience in teaching HPC techniques to students and scientists from computational science and engineering programs. His research interests include solving large sparse eigenvalue problems, novel parallelization approaches, hybrid parallel programming, performance engineering for numerical applications, and architecture-specific optimization.

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