Tuesday Keynote
Moore’s Law 2020 

tl_files/isc/images/content/program/Pawlowski_140x160px.jpg

Tuesday, June 18, 5:15 pm - 6:00 pm, Hall 1

Stephen S. Pawlowski
Senior Fellow, Chief Technology Officer for the Datacenter & Connected Systems Group (DCSG) & General Manager for the Architecture Group & DCSG Pathfinding, Intel

The past few years have seen growth in supercomputing flops that grow faster than Moore’s Law. In Phase 1 of the Moore Squared era, technology for compute density, interconnect scaling, managing software complexity and driving improved resiliency have been enabling system designers to take on designs of greater complexity and scale. In Phase 2, the complexity of systems continues to grow, but heterogeneity of system design and workload becomes part of general purpose architecture.

In this talk, Stephen Pawlowski will provide a retrospective on why not only Moore’s Law has been essential in the past, but the technologies that maintain a Moore square pace in supercomputing.  He will provide a technical vision of the technologies required to drive phase 2 of the Moore squared era that brings us through and beyond Exascale.

 

Stephen S. Pawlowski is an Intel Senior Fellow, chief technology officer for the Datacenter and Connected Systems Group (DCSG), and general manager for the Intel Architecture Group and DCSG Pathfinding for Intel Corporation. He is responsible for ensuring architectural consistency across all Intel® Architecture and implementation of initiatives such as security and manageability across Intel® Core™ and Intel® Atom™ product lines.

Pawlowski joined Intel in 1982. He led the design of the first Multibus I Single Board Computer based on the 386 processor. He was a lead architect and designer for Intel's early desktop PC and high performance server products and was the co-architect for Intel's first P6 based server chipsets. He helped define the system bus interfaces for Intel's P6 family processors, the Pentium® 4 processor and Itanium™ processor. He also created and led the research for Intel's agile radio architecture for a future generation of wireless products, he was the director of Corporate Technology Group's Microprocessor Technology Lab and prior to his current assignment, he was the CTO of the Digital Enterprise Group (DEG) and General Manager of the DEG Architecture and Planning.
Pawlowski graduated from the Oregon Institute of Technology in 1982 with bachelor's degrees in electrical engineering technology and computer systems engineering technology, and received a master's degree in computer science and engineering from the Oregon Graduate Institute in 1993.

Pawlowski holds 56 patents in the area of system, and microprocessor technologies. He has received three Intel Achievement Awards.

Platinum Sponsors

ISC Partner

Gold Sponsors